Method and apparatus for pattern sensitivity stress testing of memory systems

ABSTRACT

A method and apparatus for stress testing a computer memory system is disclosed. A sequential series of bit patterns, comprising 1&#39;s and 0&#39;s, is impressedd upon a computer memory so that, during testing, every memory cell stores a 1 while the eight adjacent neighboring memory cell stores 0&#39;s. Subsequently, the complimentary bit patterns are impressed upon memory, wherein every memory cell, at some time during the test, stores a 0 while the eight immediately adjacent neighboring memory cells store 1&#39;s. The disclosed bit pattern maximizes stress on the cells, In an interleaved dual memory bank configuration, memory cells are sequentially accessed from the highest to the lowest address of one memory bank, while memory cells are sequentially accessed from the lowest to the highest memory address in the other memory bank. Toggling successive memory accesses between the dual interleaved memory banks maximizes stress on the address driver components of the computer memory system. Preferably, the dual memory banks are simultaneously tested with complementary bit patterns to also maximize stress on the data bus driver and associated components and to maximize demand on the power supply system.

This application includes appendices entitledd: Appendix A--"Source Codefor Pattern Sensitivity Testing" including 12 pages, and AppendixB--Pseudo-Code for Pattern Sensitivity Test Process, comprising 1 page.

A portion of the disclosure of this patent document contains materialwhich is subject to copyright protection. The copyright owner has noobjection to the facsimile reproduction by anyone of the patent documentor the patent disclosure, as it appears in the Patent and TrademarkOffice patent file or records, but otherwise reserves all copyrightswhatsoever.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of testing the integrity andreliability of computer memory systems. More particularly, the presentinvention relates to stress testing modern high speed interleavedcomputer memory systems for active neighborhood pattern sensitivityfaults ("ANPSF") and passive neighborhood pattern sensitivity faults("PNPSF").

2. Description of Related Art

Solid state random access memory ("RAM") is one of the most importantcomponents of modern high speed computers. As operating systems andapplication programs become increasingly complex, they demand more andfaster RAM. Therefore, much engineering effort has been directed towardincreasing the storage capacity of RAM (i.e., increasing the number ofstorage cells in a RAM chip) while simultaneously decreasing RAM accesstimes and physical size.

Unfortunately, however, as the number of memory cells within a givenmemory chip increases, so does the probability that the chip may containa non-functioning cell. If the operating system, for example, encountersa malfunctioning memory cell, computer operation may be halted andcritical data may be lost. Failures in the components of memory addressdrivers may have similar negative consequences. Therefore, there existsa need for efficient and effective methods to locate problems with RAMmemory and associated address driver components during the computermanufacturing process, so as to eliminate, or at least minimize, memorymalfunctions during normal customer operation.

In an effort to locate non-functioning components of address drivers andmemory storage cells, and components and cells which are prone to failduring normal computer operation, test engineers have developed testswhich subject such components to stresses in excess of that which wouldbe expected during normal operation. For example, memory test algorithmswhich access memories with converging addresses stress the componentsthat address the storage cells of the memory chips. A typical test ofthis type makes its first access to the lowest memory address within thetest range, the second memory access to the highest memory addresswithin the test range, the third access to the next to lowest address,the fourth access to the next highest and so forth. Eventually, theaddresses being accessed converge at the middle of the physical memory.This method of stepping the chip addressing back and forth while thememory is under test is often referred to as "butterfly addressing."Butterfly addressing algorithms in the past were typically applied toMarch test algorithms. March test algorithms perform read/write/readoperations on each memory location as they progress through memory.Alternating the addresses in this fashion maximizes the number of 0 to 1and 1 to 0 transitions on the memory address lines, and thereforemaximizes associated power consumption and concomitant stress on thecomponents that access the memory cells.

As the physical size of RAM memory decreases, charge leakage betweenadjacent memory cells becomes the primary failure mode. Therefore,creating stress on the inter-cell physical paths between near neighborcells is a important goal of test engineers. However, because of theextremely large number of different combinations of static and dynamicstates that can exist among and between the eight cells immediatelyadjacent a target cell under test, such tests have been impossible tocompletely realize without using algorithms for addressing the memorythat degrade raw performance of a memory test to the point that the timerequired to execute the tests cannot be justified for the benefitsgained. The article by Magdy S. Abadir and Hassan K. Reghbati, ComputingSurveys, Vol 15, No. 3, September 1983, describes some of therequirements for such memory pattern sensitivity testing.

IEEE Transactions on Computers, Vol. C-26, No. 11 (November 1977), pp.1141-1144 by Knaizuk and Hartmann, discloses a test algorithm thatexploits pattern sensitivity testing in a "neighborhood of five." Theterm "neighborhood of five" refers to the total number of memory cellsinvolved in a test adjacent to and including a particular target cell.In a grid of memory cells, a neighborhood of five includes the targetcell, the cells immediately above and below the target cell and thecells immediately to the sides of the target cell. Neighborhood of fivetesting, however, fails to test for charge leakage between the targetcell and diagonally adjacent cells.

With today's memory chips achieving ever increasing higher density, thepossible leakage paths between meory cells becomes shorter and shorter.As the memory cell density increases, the probability of the most commonmemory fault becoming a leakage path to a neighboring memory cellincreases. Thus, testing of the "neighborhood of nine" memory cells forleakage between all adjacent cells, including diagonally adjacent cells,becomes very important.

SUMMARY OF THE INVENTION

This invention provides methods and apparatus for pattern sensitivityand address stress testing og memory systems. The invention provides atest procedure that accomplishes a complex but efficient "neighborhoodof nine" pattern sensitivity test. The term "neighborhood of nine"refers to the total number of nearest neighbor memory cells testedimmediately adjacent to and including a target cell. Simultaneously, theinvention stresses the system with an address stress test which producesthe stress of "butterfly addressing", but in a distinctly differentmanner. For the purpose of this disclosure (and to avoid confusion withprior art techniques) the inventive address stress testing techniquedescribed hereinafter will be referred to as "pseudo-butterflyaddressing". "Butterfly addressing" refers generally to a procedurewherein successive memory accesses are made to widely disparate physicallocations within a computer memory system.

If desired, the invention may be used to separately or simultaneously:

(1) Provide address driver and system power stress testing;

(2) Accomplish complete neighborhood of nine pattern sensitivity testingto assure that there are no passive neighborhood pattern sensitivityfaults;

(3) Detect active neighborhood pattern sensitivity faults withoutjeopardizing the viability of the test algorithm from excessivecomplexity or long run time; and

(4) Provide a test algorithm uniquely suited to a multi-bank interleavedcomputer memory system.

This invention may be used to test for both Passive Neighborhood PatternSensitivity Faults (PNPSF) and Active Neighborhood Pattern SensitivityFaults (ANPSF). ANPSF refers to faults which result from a change in thestate of a memory cell. PNPSF refers to memory cell malfunctions whichoccur because of a particular static memory pattern impressed upon amemory chip.

The inventive neighborhood of nine pattern sensitivity test stresses agiven target cell with eight neighbor memory cells that are in theopposite state, so as to provide the maximum charge differential betweenthe target cell and the eight nearest neighbor adjacent cells, andthereby the greatest opportunity for charge leakage.

For a method viewpoint, the invention involves the following steps:

(1) Write to the target cell to see if a write operation to that cell ispossible, and that it does not create a disturbance (i.e., a change instate) in any of the eight nearest neighbor cells:

(2) Read the target cell's eight nearest neighbors to detect anydisturbance caused by the write operation to the target cell and also totest the possibility that reading a neighbor cell might disturb thetarget cell; and

(3) Read the target cell to verify that no disturbance occurred whilereading the target cells eight nearest neighbors.

From a first alternative method viewpoint, the invention involves thefollowing steps:

(1) Write a specific pattern to all eight neighbor cells in aneighborhood of nine cells;

(2) Write all target cells to a compliment pattern (where 0 is thecomplement of 1 and 1 is the complement of 0);

(3) Read all neighborhood cells to see if the target cell writes createdany disturbance in the neighborhood;

(4) Read all target cells to see if reading the neighbor cells disturbedany target cells; and

(5) Repeat each of steps 1-4 until all possible cells of a neighborhoodof nine cells become a target cell, thereby testing for the ability ofeach cell to hold either a 0 or a 1 while the maximum charge disturbanceis created in the neighborhood of each such target cell.

(6) Repeat steps (1) through (5) with the complimentary pattern of 0sand 1s.

The invention requires 12 iterations of steps 1 through 4 above tocompletely test all static pattern combinations.

From a third alternative method viewpoint, when the invention is used ina memory system having multiple (for example, two) banks of interleavedphysical memory units, the test sequence in the pattern sensitivitystress test for interleaved memory includes the following steps:

(1) Write all memory including both target (foreground) cells andneighbor (background) cells to the same state to validate memory;

(2) Write the target cell of each modulo 6 frame to attempt to disturbits nearest eight neighbors. The writes are accomplished during a scanof one memory bank from the lowest target memory cell address ascendingto the highest target memory cell address. The other memory bank beingsimilarly scanned from the highest to lowest target cell address, whilealternating memory accesses between memory banks. (Note that this steponly requires writing one sixth of the memory under test);

(3) Read the eight neighbor (background) cells immediately adjacent toeach target (foreground) cell, scanning one memory bank from the lowestmemory address ascending to the highest memory address, alternatingbetween accesses to each memory bank, the other memory bank beingscanned from the highest memory address descending to the lowest memoryaddress. Toggling accesses between the two memory banks using thispseudo-butterfly addressing technique maximizes stress on the addressdrivers and the system power source. Unlike the prior technique,however, the addresses do not converge in the middle of a singlephysical memory chip. This read of the entire memory is done to detectany cell disturbance in either the target (foreground) or neighbor(background) cells. During this time the invention may, if desired,utilize error correction code (ECC) to detect single bit correctableerrors in a manner known in the art. In all cases target (foreground)and neighbor (background) cells should preferably contain data that is acomplement of the other;

(4) Restore the target (foreground) cells to the same pattern as theneighbor (background) cells. Again, this only requires writing one sixthof the memory under test. If the sixth cell of the modulo 6 memory frameis currently the target, the entire memory is written to the complementof the neighbor (background) state;

(5) Sequence to the next sequential cell within the modulo 6 memoryframe or start over with the complementary test pattern if all six cellsof the modulo 6 memory frame have been tested; and

(6) After sequencing to the next cell target, perform the precedingsteps 2 through 5.

All six cells of the modulo 6 memory frame are tested in the abovemanner twice, once to test with target cells as 1's, and once to testtarget cells as 0's. Therefore, twelve iterations of the above processare needed to target each cell both in a neighborhood of 1's and in aneighborhood of 0's.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described with reference to the accompanyingdrawings, wherein:

FIG. 1 illustrates a computer memory system, including a memorycontroller having an address driver, data bus driver and two interleavedsolid state RAM memory chips.

FIGS. 2-7 sequentially illustrate the bit pattern progression in a small16×16 memory cell array using the neighborhood of nine test sequence,wherein the 1 bits are the "foreground" or target bits and the 0 bitsform the "background" or non-target bits.

FIGS. 8-13 illustrate the complimentary bit pattern progression in thesame small 16×16 memory cell, wherein the 0 bits comprise the"foreground" or target bits and the 1 bits comprise the "background" ornon-target bits.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following description is of the best presently contemplated modes ofcarrying out the invention. This description is made for the purpose ofillustrating the general principles of the invention and is not to betaken in a limiting sense.

FIG. 1 illustrates the architecture of a computer memory system 10utilizing interleaved dual memory banks 12, 14. In accordance with amethod known to those trained in the computer memory field, a memorycontroller 15 including an address driver 16 transmits signals alongaddress lines 18 in response to instructions from CPU 20. As memorycells 22 are addressed, in accordance with signals from address driver16, each memory cell 22 is read from and written to via signalstransmitted along the data bus 21 from the data bus driver 24 also in amanner known to those trained in the computer memory field.

Memory accesses require a certain fixed set-up time and, therefore, manyhigh speed computer memory systems now use "interleaved memory," whereinsequential memory accesses occur first to one memory bank 12 then to theother memory bank 14. In this way, memory access times are effectivelydecreased since a memory read or write operation can take place in onememory bank 12 while the other memory bank 14 is being set up for thenext succeeding memory access.

FIGS. 2-13 illustrate a preferred embodiment of the present inventionoperative in a small 16×16 memory celll array. The 16×16 array is usedfor illustrative purposes; practical computer memories, of course, tendto be significantly larger.

In the 16×16 cell array illustration, FIGS. 2-13 show the twelvesequential patterns written into the array. One can readily see how theeight neighbors of a given target cell are in the opposite state fromthe target cells. The cells containing 1's are totally surrounded by0's, even in locations that are on diagonals from the target cells. Thatis, each of eight neighbors in the neighborhood of nine cells are of theopposite state from the target cells. With the twelve patterns of thetest, each cell in the array in turn becomes surrounded with cells ofthe opposite state, for both the 0's and 1's cases. The illustrations ofFIGS. 2-13 shows the contents of a bit slice one bit wide in one bank ofthe memory under test. A 16×16 memory was chosen for illustration ease,although the same principle applies to memory arrays of any size thatare addressed modulo two.

The algorithm specifically described herein is implemented for a twobank interleaved memory system, as shown in FIG. 1, but is readilyadaptable to non-interleaved memory systems or memory systems withinterleave greater than two.

Passive Pattern Testing:

As illustrated b the vertical dashed lines in FIG. 2, a neighborhood ofnine test scenario can be developed in a memory system that is addressedmodulo 2 by subdividing memory horizontally into groups of cells modulo6. A modulo 6 cell group may be referred to in this description of thetest algorithm as a "frame". The specific cell under test is referred toas the target cell.

With reference to FIG. 2, the initial test pattern puts a 1 into thefirst target cell of each frame and 0's into each of the other fivecells of the frame. Imaginary squares 32 illustratively surround threeneighborhoods of nine adjacent memory cells. To cover the possibilitiesof each cell within a frame being a 1 with the other eight cells being0's requires storing six different pattern sequences into memory. FIG.3-7 illustrate each of these subsequent sequences. Six additionalsequences, illustrated in FIGS. 8-13, are required to make each cellwithin a frame be a 0 with 1's in the other five cells of the frame. Atotal of twelve test sequences, with the unique patterns illustrated inFIGS. 2-13 collectively, are required to make each of the cells of the"neighborhood of nine" become a target cell holding a 0 and a 1.

The process for impressing the various illustrated memory patterns on tothe memory banks 12,14 is driven by a software program which runs on aCPU 20 (FIG. 1). The instructions comprising this program are preferablystored in cache memory 34 separate from the memory 12,14 under test. TheCPU 20 provides instructions to the address driver 16 and to a data busdriver 24 to cause memory I/O to be performed on each of the memorycells 22 under control of the software program.

A presently preferred program for accomplishing the memory test processdisclosed herein is contained in Appendix A attached hereto andincorporated herein by reference. This program is written in C computerprogramming language and will be readily understood by one of ordinaryskill in the relevant technological field. To further elucidate apresently preferred embodiment of the subject invention, Appendix B,which is also attached hereto and incorporated herein by reference,contains pseudo code for the stress testing process.

As implemented by the software program of Appendix A, the memory testprocedure includes the major steps of:

(1) Writing all 0's into both memory banks:

(2) Write a 1 into each group of modulo 6 memory cells in one of thememory banks according to the bit pattern illustrated in FIGS. 2-7 andin a first direction of memory addresses (e.g., increasing memoryaddresses) and write the same bit pattern into the other memory bank,except in the reverse direction of memory addresses;

(3) Truncate the bit pattern at the end of memory if the end of memorydoes not coincide exactly with the end of a pattern sequence;

(4) Read all of memory and compare the originally written pattern withthe pattern as now read;

(5) If any miscompares are located, the software logs an error so thatappropriate action may be taken. Depending upon the circumstances, andseverity of the problem, the test technician may replace the memorychip, address driver or other failed component, or the CPU may beinstructed to avoid the page of memory containing the failed memorycell.

(6) Write one-sixth of memory by overwriting all 1's with 0's.

(7) Re-write the original pattern of 1's and 0's into memory, but inthis step the modulo 6 bit pattern is shifted by one memory cell. (Againony one-sixth of memory is written, thereby making this processexceptionally fast).

(8) Read the entire memory looking for miscompares between the patternwritten in step 7 above and the pattern read in this step 8 and reportany problems for appropriate action.

(9) Repeat steps 2-8 until all memory cells are written with a 1.

(10) Repeat steps 1 through 9 with the complementary bit pattern.

(11) Alternate all memory accesses between the two interleaved memorybanks according to the previously described pseudo-butterfly addressingtechnique such that, at any one time, the two memory banks are beingtested with complementary patterns--i.e., one memory bank contains a bitpattern composed predominantly of 1's and the other memory bank containsa bit pattern composed primarily of 0's.

Pseudo-Butterfly Stress Testing:

An important aspect of this invention in some preferred embodiments isthat the process may be run on a multi-bank (interleaved) memory system.Interleaved memory systems are necessary to achieve the high memory busdata rates required by today's high performance computers.

An aspect of certain specific preferred embodiments of the presentinvention includes the use of a type of butterfly addressing technique.This memory test process simultaneously undertakes to perform a patternsensitivity test that stresses paths to the nearest eight neighbors of agiven memory cell (neighborhood of nine), as set forth previously, whilesimultaneously gaining the benefits of additional stress testing byalternately addressing multiple memory banks--one memory banksequentially from the highest address to the lowest address whilealternately accessing the other memory bank from the lowest address tothe highest address. This aspect of the invention thus succeeds incombining the stress induced by previously known "butterfly addressing"sequences (but in a very different way) with a complex "neighborhood ofnine" pattern sensitivity test.

The process implemented by the software program of Appendix A isoptimized for a two bank memory system such as that shown in FIG. 1.,wherein one of the memory banks, e.g. 12, is tested (i.e., addressedduring the test) sequentially from the lowest address toward the highestaddress. The other of the two memory banks, e.g., 14, is tested from thehighest address toward the lowest address.

It will be understood that, since the presently preferred embodimentduscussed herein is implemented in an interleaved dual memory bankmemory system, the "pseudo-butterfly addressing" sequence discussedherein differs significantly from the butterfly addressing techniquesdiscussed previously. In particular, wherein in prior techniquessubsequent memory accesses alternated between low and high memoryaddresses and ultimately converged at a memory address in the middle ofa single memory chip, the present addressing technique sweepscontinuously from a high memory address to a low memory address of asingle memory chip. However, from the point of view of an addressdriver, sequential memory accesses occur first to one memory bank andsubsequently to another and different alternate interleaved memory bank.Increased stress on the memory driver components, however, is achievednotwithstanding a continuously increasing or decreasing memory addressaccess to a single memory bank because sequential memory accesses occurbetween different memory banks and the different memory banks arealternately accessed from a high to low memory address and from a low tohigh memory address, respectively. Thus, address driver outputapproaches the maximum stress condition of a simultaneously switchedoutputs ("SSO").

In some systems pseudo-butterfly addressing will induce a considerableincrease in overall noise in the power supply because of the increasedswitching which is induced in the output of the address driver 16 anddata bus driver 21. In a worst case scenario pseudo-butterfly addressingmay even cause noticeable "ground shift" in the power system. In anyevent, the results of the pattern sensitivity stress testing disclosedherein may be useful to test engineers in improving the design of thecomputer memory and power systems, as well as in locating single faultsin memory chips.

Several preferred embodiments of the present invention have beendescribed. Nevertheless, it will be understood that variousmodifications may be made without departing from the spirit and scope ofthe invention. For example, the invention may be utilized in interleavedcomputer memory systems having more than two interleaved memory banks.Alternatively, the method and apparatus of the present invention may beadapted for use in a computer system having a single memory bank.Furthermore, patterns other than those specifically disclosed aspreferred in the application may be used to create stress in a computermemory subsystem so as to assist in the identification of existingfaults and the identification of components likely to fail during normaluse of the computer. Memory protected by an eror correcting code (ECC),although helpful, is not an essential component of the inventionsdescribed herein. The pseudo-butterfly memory accessing techniquedescribed herein may be used during some or all memory access passesthrough memory in an interleaved computer memory system. Thus, thepresent invention is not limited to the preferred embodiments describedherein, but may be altered in a variety of ways which will be apparentto persons skilled in the art.

List of Appendices

Appendix A--"C Language Source Code Listing For Pattern SensitivityTesting"

Appendix B--"Pseudo-code For Pattern Sensitivity Testing Process"##SPC1##

What is claimed is:
 1. A method for stress testing a memory systemhaving a plurality of memory cells capable of being grouped in aplurality of neighborhoods of nine cells, each neighborhood of ninecells including a center cell and eight cells surrounding the centercell, the method comprising the steps of:(a) writing all of the memorycells within a predetermined address range of the memory system with afirst value; (b) writing a plurality of target cells with a second valuewhich is a complement of the first value, each of the target cells beinga center cell of each of a first group of neighborhoods of nine cellswithin the address range, each of the target cells being surrounded byeight non-target cells; (c) reading all of the non-target cells withinthe address range and reporting a failure condition if any non-targetcells contain other than the first value; and (d) reading all of thetarget cells and reporting a failure condition if any target cellscontain other than the second value.
 2. The method of claim 1, furthercomprising the step of repeating the steps (a) to (d) until all of thecells within the address range have been written as target cells of aplurality groups of neighborhoods of nine cells.
 3. The method of claim2, further comprising the step of repeating the steps (a) to (d) withthe second value written to all of the plurality of memory cells whenthe step (a) is performed and the first value written to the pluralityof target cells when the step (b) is performed.
 4. A system for stresstesting a computer memory system having a plurality of memory cellsarranged in a matrix pattern, comprising:means for writing to a targetcell within a neighborhood of 9 cells; first means for reading thetarget cells 8 nearest neighbors, detecting a disturbance in the targetcells 8 nearest neighbors and determining if the write to the targetcells caused the disturbance; second means for reading the target celland determining whether a disturbance occurred in the target cell whilethe first means for reading read the 8 nearest neighbor cells.
 5. Asystem for stress testing a memory system having a plurality of memorycells capable of being grouped in a plurality of neighborhoods of ninecells, each neighborhood of nine cells including a center cell and eightcells surrounding the center cell, the system comprising:first writingmeans for writing all of the memory cells within a predetermined addressrange of the memory system with a first value; second writing means forwriting a plurality of target cells with a second value which is acomplement of the first value, each of the target cells being a centercell of each of a first group of neighborhoods of nine cells within theaddress range, each of the target cells being surrounded by eightnon-target cells; first reading means for reading all of the non-targetcells within the address range and reporting a failure condition if anynon-target cells contain other than the first value; and second readingmeans for reading all of the target cells and reporting a failurecondition if any target cells contain other than the second value. 6.The system of claim 5, further comprising means for causing the firstand second writing means and the first and second reading means torepeat performing the writing and reading functions, respectively untilall of the cells within the address range have been written as targetcells of a plurality groups of neighborhoods of nine cells.
 7. Thesystem of claim 6, further comprising means for causing the first andsecond writing means and the first and second reading means to repeatperforming the writing and reading functions, respectively with thefirst writing means writing the second value to all of the plurality ofmemory cells and the second writing means writing the first value to theplurality of target cells.
 8. A computer program product comprising:acomputer usuable medium having computer readable code embodied thereinfor stress testing a memory system having a plurality of memory cellscapable of being grouped in a plurality of neighborhoods of nine cells,each neighborhood of nine cells including a center cell and eight cellssurrounding the center cell, the computer program product comprising:computer readable program code devices configured to cause a computereffect performing a first writing function by writing all of the memorycells within a predetermined address range of the memory system with afirst value; computer readable program code devices configured to causea computer effect performing a second writing function by writing aplurality of target cells with a second value which is a complement ofthe first value, each of a first group of target cells being a centercell of each of a first group of neighborhoods of nine cells within theaddress range, each of the target cells being surrounded by eightnon-target cells; computer readable program code devices configured tocause a computer effect performing a first reading function by readingall of the non-target cells within the address range and reporting afailure condition if any non-target cells contain other than the firstvalue; and computer readable program code devices configured to cause acomputer effect performing a second reading function by reading all ofthe target cells and reporting a failure condition if any target cellscontain other than the second value.
 9. The computer program product ofclaim 8, further comprising computer readable program code devicesconfigured to cause a computer to effect repeating performing the firstand second writing functions and the first and second reading functionsuntil all of the cells within the address range have been written astarget cells of a plurality groups of neighborhoods of nine cells. 10.The computer program product of claim 9, further comprising the computerreadable program code devices configured to cause a computer to effectrepeating performing the first and second writing functions and thefirst and second reading functions, with the second value written to allof the plurality of memory cells and the first value written to theplurality of target cells.